SC28L198

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Receiver flow control causes the Transmitter to emit an Xoff mode.
Table 4. MR1 Mode Register 1
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Bit 7 Bit 6 Bit 5 Bit 4:3 Bit 2 Bit 1:0
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RxRTS ISR Read Mode Error Mode Parity Mode Parity Type Bits per Charac-
Control � � � � ��
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0 off 0 ISR unmasked 0 = Character 00 With Parity 0 = Even 00 5
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1 on 1 ISR masked 1 = Block 01 Force parity 1 = Odd 01 6
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10 No parity 10 7
��11 8
� � �1 Special Mode � ��
1
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MR1[7]: Receiver Request to Send Control This bit controls the readout mode of the Interrupt Status Register,
This bit controls the deactivation of the RTSN output (I/O2) by the ISR. If set, the ISR reads the current status masked by the IMR, i.e.
receiver. This output is asserted and negated by commands applied only interrupt sources enabled in the IMR can ever show a 1 in the
via the command register. MR1[7] = 1 causes RTSN to be ISR. If cleared, the ISR shows the current status of the interrupt
automatically negated upon receipt of a valid start bit if the receiver source without regard to the Interrupt Mask setting.
FIFO is full or greater. RTSN is reasserted when an the FIFO fill
MR1[5]: Error Mode Select
level falls below full. This constitutes a change from previous
This bit selects the operating mode of the three FIFOed status bits
members of Philips (Signets) UART families where the RTSN
(FE, PE, received break). In the character mode, status is provided
function triggered on FIFO full. This behavior caused problems with
on a character by character basis; the status applies only to the
PC UARTs that could not stop transmission at the proper time. .
character at. the bottom of the FIFO. In the block mode, the status
The RTSN feature can be used to prevent overrun in the receiver, by
provided in the SR for these bits is the accumulation (logical OR) of
using the RTSN output signal, to control the CTSN input of the
the status for all characters coming to the top of the FIFO, since the
transmitting device.
last reset error command was issued.
MR1[6]: Interrupt Status Masking MR1[4:3]: Parity Mode Select
1999 Jan 14 19
Philips Semiconductors Product specification
Octal UART for 3.3V and 5V supply voltage SC28L198
If with parity or force parity is selected, a parity bit is added to the parity mode is programmed. In the special wake up mode, it
transmitted character and the receiver performs a parity check on selects the polarity of the A/D bit. The parity bit is used to an
incoming data. MR1[4:3] = 11 selects the channel to operate in the address or data byte in the wake up mode.
special wake up mode.
MR1[2]: Parity Type Select MR1[1:0]: Bits per Character Select
This bit sets the parity type (odd or even) if the with parity mode is This field selects the number of data bits per character to be
programmed by MR1[4:3], and the polarity of the forced parity bit if transmitted and received. This number does not include the start,
the force parity mode is programmed. It has no effect if the no parity, or stop bits.
Table 5. MR2 Mode Register 2
The MR2 register provides basic channel setup control that may need more frequent updating.
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Bits 7:6 Bit 5 Bit 4 Bit 3:2 Bit 1:0
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Channel Mode TxRTS Control CTSN Enable Tx RxINT Stop Length
00 = normal 0 = No 0 = No 00 = RRDY 00 = 1.0
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01 = Auto echo 1 = Yes 1 = Yes 01 = Half Full 01 = 1.5
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10 = Local loop 10 = 3/4 Full 10 = 2.0
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11 = Remote loop 11 = Full 11 = 9/16
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MR2[7:6] Mode Select The received parity is not checked and is not regenerated for
transmission, i.e., the transmitted parity bit is as received.
The Octal UART can operate in one of four modes: MR2[7:6] = b 00
is the normal mode, with the transmitter and receiver operating The receiver must be enabled, but the transmitter need not be
enabled.
independently.
Character framing is not checked, and the stop bits are
MR2[7:6] = b 01 places the channel in the automatic echo mode,
re-transmitted as received.
which automatically re transmits the received data. The following
A received break is echoed as received until the next valid start
conditions are true while in automatic echo mode:
bit is detected.
Received data is re clocked and re transmitted on the TxD
MR2[5] Transmitter Request to Send Control
output.
This bit controls the deactivation of the RTSN output (I/O2) by the
The receive clock is used for the transmitter.
transmitter. This output is manually asserted and negated by
The receiver must be enabled, but the transmitter need not be
appropriate commands issued via the command register. MR2[5] =
enabled.
1 causes RTSN to be reset automatically one bit time after the
The TxRDY and TxEMT status bits are inactive.
characters in the transmit shift register and in the TxFIFO (if any)
The received parity is checked, but is not regenerated for
are completely transmitted (includes the programmed number of
transmission,
stop bits if the transmitter is not enabled). This feature can be used
i.e., transmitted parity bit is as received.
to automatically terminate the transmission of a message as follows:
Character framing is checked, but the stop bits are re-transmitted
Program auto reset mode: MR2[5]= 1.
as received.
Enable transmitter.
A received break is echoed as received until the next valid start
Assert RTSN via command.
bit is detected
Send message.
After the last character of the message is loaded to the TxFIFO,
. CPU to receiver communication continues normally, but the CPU
disable the transmitter. Before disabling the transmitter be sure
to transmitter link is disabled.
the Status Register TxEMT bit is NOT set (i.e., the transmitter is
not underrun). The underrun condition is indicated by the
Two diagnostic modes can also be selected. [ Pobierz całość w formacie PDF ]

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